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i 2 c ? cmos 8 10 unbuffered analog switch array with dual/single supplies data sheet adg2108 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents o r other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are t he property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 C 2012 analog devic es, inc. all rights reserved. features i 2 c - compatible interface 3.4 mhz high speed i 2 c option 32- lead lfcsp_ w q (5 mm 5 mm) double - buffered input logic simultaneous update of multiple switches up to 300 mhz bandwidth fully specified at dual 5 v / single +12 v operation on resistance 3 5 ? maximum low quiescent current < 20 a applications av switching in tv automotive infotainment av receivers cctv ultrasound applications kvm switching telecom applications test equipment/instrumentation pbx systems g eneral description the adg2108 is an analog cross point switch with an array size of 8 10. the switch array is arranged so that there are eight columns by 10 rows, for a total of 80 switch channels. the array is bidirectional, and the rows and columns can be configured as either inputs or outputs. each of the 80 switches can be addressed and configured through the i 2 c - compatible interface. standard, full speed , and high s peed (3.4 mhz) i 2 c interfaces are supported. any simultaneous switch combination is allowed . an additional feature of the adg2108 is that switches can be updated simultaneously, using the ldsw command. in addition, a reset option allows all of the switch channels to be reset/off. at power on, all switches are in the off condition. the device is packaged in a 32 - lead, 5 mm 5 mm lfcsp_ w q. f unctional block diag ram adg2108 v dd v ss v l scl sda x0 to x9 (i/o) 8 10 switch array ldsw 80 1 80 1 input register and 7 to 80 decoder latches ldsw gnd a0 a1 a2 y0 to y7 (i/o) 05898-001 figure 1 .
adg2108 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 i 2 c timing specifications ............................................................ 7 timing diagram ........................................................................... 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin c onfiguration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 test circuits ..................................................................................... 15 terminology .................................................................................... 17 theory of operation ...................................................................... 18 reset /power - on reset ............................................................ 18 load switch (ldsw) ................................................................. 18 readback ..................................................................................... 18 serial interface ................................................................................ 19 high speed i 2 c interface ........................................................... 19 serial bus address ...................................................................... 19 writing to the adg2108 ............................................................... 20 input shift register .................................................................... 20 write operation .......................................................................... 22 read operation ........................................................................... 22 evaluation board ............................................................................ 24 using the adg2108 evaluation board ................................... 24 power supply ............................................................................... 24 schematics ................................................................................... 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 9/12 rev a to rev. b changes to figure 37 ....................................................................... 26 changes to ordering guide ........................................................... 27 8 /12 rev. 0 to rev. a changed cp - 32 - 2 package to cp - 32- 7 package ............. universal updated outline dimensions ...................................................... 27 changes to ordering guide .......................................................... 27 4 /06 revis ion 0: initial version
data sheet adg2108 rev. b | page 3 of 28 specifications v dd = 12 v 10% , v ss = 0 v, v l = 5 v, gnd = 0 v, all specifications t min to t max, unless otherwise noted. 1 table 1. parameter b version y version unit conditions +25c ?40c to +85c +25c ?40c to +125c analog switch analog signal range v dd ? 2 v v dd ? 2 v v max on resistance, r on 30 30 ? typ v dd = 10.8 v, v in = 0 v, i s = ?10 ma 35 40 35 42 ? max 32 32 ? typ v dd = 10.8 v, v in = 1.4 v, i s = ?10 ma 37 42 37 47 ? max 45 45 ? typ v dd = 10.8 v, v in = 5.4 v, i s = ?10 ma 50 57 50 62 ? max on resistance matching 4.5 4.5 ? typ v dd = 10.8 v, v in = 0 v, i s = ?10 ma between channels, ?r on 8 9 8 10 ? max on resistance flatness, r flat(on) 2.3 2.3 ? typ v dd = 10.8 v, v in = 0 v to 1.4 v, i s = ?10 ma 3.5 4 3.5 5 ? max 14.5 14.5 ? typ v dd = 10.8 v, v in = 0 v to 5.4 v, i s = ?10 ma 18 20 18 22 ? max leakage currents v dd = 13.2 v channel off leakage, i off 0.03 0.03 a typ v x = 7 v /1 v, v y = 1 v/7 v channel on leakage, i on 0.03 0.03 a typ v x = v y = 1 v or 7 v dynamic characteristics 2 c off 11 11 pf typ c on 18.5 18.5 pf typ t on 170 170 ns typ r l = 300 ?, c l = 35 pf 185 190 185 195 ns max t off 210 2 10 ns typ r l = 300 ?, c l = 35 pf 250 255 250 260 ns max thd + n 0.04 0.04 % typ r l = 10 k ? , f = 20 hz to 20 khz, v s = 1 v p -p psrr 90 db typ f = 20 khz; without decoupling; see figure 24 ?3 db bandwidth 210 210 mhz typ individual inputs to outputs 16.5 16.5 mhz typ 8 inputs to 1 output off isolation ?69 ?69 db typ r l = 75 ?, c l = 5 pf, f = 5 mhz channel -to - channel crosstalk r l = 75 ?, c l = 5 pf, f = 5 mhz adjacent c hannels ?63 ?63 db typ nonad jacent c hannels ?76 ?76 db typ differential gain 0.4 0.4 % typ r l = 75 ?, c l = 5 pf, f = 5 mhz differential phase 0.6 0.6 typ r l = 75 ?, c l = 5 pf, f = 5 mhz charge injection ?3.5 ?3.5 pc typ v s = 4 v, r s = 0 ?, c l = 1 nf logic inputs (ax, reset ) 2 input high voltage, v inh 2.0 2.0 v min input low voltage, v inl 0.8 0.8 v max input leakage current, i in 0.005 0.005 a typ 1 1 a max input capacitance, c in 7 7 pf typ
adg2108 data sheet rev. b | page 4 of 28 parameter b version y version unit conditions +25c ?40c to +85c +25c ?40c to +125c logic inputs (scl, sda) 2 input high voltage, v inh 0.7 v l 0.7 v l v min v l + 0.3 v l + 0.3 v max input low voltage, v inl ?0.3 ?0.3 v min 0.3 v l 0.3 v l v max input leakage current, i in 0.005 0.005 a typ v in = 0 v to v l 1 1 a max input hysteresis 0.05 v l 0.05 v l v min input capacitance, c in 7 7 pf typ logic output (sda) 2 output low voltage, v ol 0.4 0.4 v max i sink = 3 ma 0.6 0.6 v max i sink = 6 ma floating state leakage current 1 1 a max power requirements i dd 0.05 0.05 a typ digital i nputs = 0 v or v l 1 1 a max i ss 0.05 0.05 a typ digital inputs = 0 v or v l 1 1 a max i l digital inputs = 0 v or v l interface i nactive 0.3 0.3 a typ 2 2 a max interface a ctive: 400 khz f scl 0.1 0.1 ma typ 0.2 0.2 ma max interface a ctive: 3.4 mhz f scl 0.4 0.4 ma typ - hs model only 1.2 1.7 ma max 1 temperature range is as follows: b version: ?40c to +85c; y version: ?40c to +125c. 2 guaranteed by design, not subject to production test.
data sheet adg2108 rev. b | page 5 of 28 v dd = +5 v 10% , v ss = ?5 v 10% , v l = 5 v, gnd = 0 v, all specifications t min to t max , unless otherwise noted. 1 table 2. b version y version parameter +25c ?40c to +125c +25c ?40c to +125c unit conditions analog switch analog signal range v dd ? 2 v v ma x on resistance, r on 34 34 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = v ss , i s = ?10 ma 40 45 40 50 ? max 50 50 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = 0 v, i s = ?10 ma 55 65 55 70 ? max 66 66 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = 1.4 v, i s = ?10 ma 75 85 75 95 ? max on resistance matching 4.5 4.5 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = v ss , i s = ?10 ma between channels, ?r on 8 9 8 10 ? max o n resistance flatness, r flat(on) 17 17 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = v ss to 0 v, i s = ?10 ma 20 23 20 25 ? max 34 34 ? typ v dd = +4.5 v, v ss = ?4.5 v, v in = v ss to 1.4 v, i s = ?10 ma 42 45 42 48 ? max leakage currents v dd = 5.5 v, v ss = 5.5 v channel off leakage, i off 0.03 0.03 a typ v x = +4.5 v/?2 v, v y = ?2 v/+4.5 v channel on leakage, i on 0.03 0.03 a typ v x = v y = ?2 v or +4.5 v dynamic characteristics 2 c off 6 6 pf typ c on 9.5 9.5 pf typ t on 170 170 ns typ r l = 300 ?, c l = 35 pf 200 215 200 220 ns max t off 210 210 ns typ r l = 300 ?, c l = 35 pf 250 255 250 260 ns max thd + n 0.04 0.04 % typ r l = 10 k ? , f = 20 hz to 20 khz, v s = 1 v p -p psrr 90 db typ f = 20 khz; without decou pling; see figure 24 ?3 db bandwidth 300 300 mhz typ individual inputs to outputs 18 18 mhz typ 8 inputs to 1 output off isolation ?66 ?64 db typ r l = 75 ?, c l = 5 pf, f = 5 mhz channel - to - channel crosstalk r l = 75 ?, c l = 5 pf, f = 5 mhz adjacent c hannels ?62 ?62 db typ nonadjacent c hannels ?79 ?79 db typ differential gain 1.5 1.5 % typ r l = 75 ?, c l = 5 pf, f = 5 mhz differential phase 1.8 1.8 typ r l = 75 ?, c l = 5 pf, f = 5 mhz charge inject ion ?3 ?3 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf logic inputs (ax, reset ) 2 input high voltage, v inh 2.0 2.0 v min input low voltage, v inl 0.8 0.8 v max input leakage current, i in 0.005 0.005 a typ 1 1 a max input capacitance, c in 7 7 pf typ logic inputs (scl, sda) 2 input high voltage, v inh 0.7 v l 0.7 v l v min v l + 0.3 v l + 0.3 v max input low voltage, v inl ?0.3 ? 0.3 v min 0.3 v l 0.3 v l v max
adg2108 data sheet rev. b | page 6 of 28 b version y version parameter +25c ?40c to +125c +25c ?40c to +125c unit conditions input leakage current, i in 0.005 0.005 a typ v in = 0 v to v l 1 1 a max input hysteresis 0.05 v l 0.05 v l v min input capacitance, c in 7 7 pf typ logic output (sda) 2 output low voltage, v ol 0.4 0.4 v max i sink = 3 ma 0.6 0.6 v max i sink = 6 ma floating state leakage current 1 1 a max power requirements i dd 0.05 0.005 a typ digital inputs = 0 v or v l 1 1 a max i ss 0.05 0.005 a typ digital inputs = 0 v or v l 1 1 a max i l digital inputs = 0 v or v l interface i nactive 0.3 0.3 a typ 2 2 a max interface active: 400 khz f scl 0.1 0.1 ma typ 0.1 0.1 ma max interface active: 3.4 mhz f sc l 0.4 0.4 ma typ - hs m odel only 0.3 0.3 ma max 1 temperature range is as follows: b version: C 40c to +85c; y version: C 40c to +125c. 2 guaranteed by design, not subject to production test.
data sheet adg2108 rev. b | page 7 of 28 i 2 c timing specifications v dd = 5 v to 12 v; v ss = ?5 v to 0 v; v l = 5 v; gnd = 0 v; t a = t min to t max , unless otherwise noted (see figure 2 ). table 3. adg2108 limit at t min , t max parameter 1 conditions min max unit description f scl standard mod e 100 khz serial clock frequency fast mode 400 khz high speed mode 2 c b = 100 pf maximum 3.4 mhz c b = 400 pf maximum 1.7 mhz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode 2 c b = 100 pf maximum 60 ns c b = 400 pf maximum 120 ns t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s high speed mode 2 c b = 100 pf maximum 160 ns c b = 400 pf maximum 320 ns t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 2 10 ns t 4 3 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s high speed mode 2 c b = 100 pf maximum 0 70 ns c b = 400 pf maximum 0 150 ns t 5 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s high speed mode 2 160 ns t 6 standard mode 4 s t hd;sta , hold ti me for a repeated start condition fast mode 0.6 s high speed mode 2 160 ns t 7 standard mode 4.7 s t buf , bus free time betwe en a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s high speed mode 2 160 ns t 9 standard mode 1000 ns t rda , rise time o f sda signal fast mode 20 + 0.1 c b 300 ns high speed mode 2 c b = 100 pf maximum 10 80 ns c b = 400 pf maximum 20 160 ns t 10 standard mode 300 ns t fda , fall time of sda signal fast mode 20 + 0.1 c b 300 ns high speed mode 2 c b = 100 pf maximum 10 80 ns c b = 400 pf maximum 20 160 ns
adg2108 data sheet rev. b | page 8 of 28 adg2108 limit at t min , t max parameter 1 conditions min max unit description t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 20 + 0.1 c b 300 ns high speed mode 2 c b = 100 pf maximum 10 40 ns c b = 400 pf maximum 20 80 ns t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated start fast mode 20 + 0.1 c b 300 ns condition and after an acknowledge bit high speed mode 2 c b = 100 pf maximum 10 80 ns c b = 400 pf maximum 20 160 ns t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 20 + 0.1 c b 300 ns high speed m ode 2 c b = 100 pf maximum 10 40 ns c b = 400 pf maximum 20 80 ns t sp fast mode 0 50 ns pulse width of suppressed spike high speed mode 2 0 10 ns 1 guaranteed by initial characterization. all values measured with input filtering enabled. c b refers to capacitive load on the bus line; t r and t f are measured between 0.3 v dd and 0.7 v dd . 2 high speed i 2 c is available only in - hs models. 3 a device must provide a data hold time for sda to bridge the undefined region of the scl falling edge. timing diagram p s s p sda scl s = start condition p = stop condition t 7 t 6 t 4 t 2 t 11 t 12 t 1 t 3 t 5 t 6 t 10 t 8 t 9 05898-002 figure 2 . timing diagram for 2 - wire serial interface
data sheet adg2108 rev. b | page 9 of 28 absolute maximum rat ings t a = 25c , unless otherwise noted. table 4. parameter rating v dd to v ss 15 v v dd to gnd ?0.3 v to +15 v v ss to gnd +0.3 v to ?7 v v l to gnd ?0.3 v to +7 v analog inputs v ss ? 0.3 v to v dd + 0.3 v digital inputs ?0.3 v to v l + 0.3 v or 30 ma, whichever occurs first continuous current 10 v on input; single input connected to single outp ut 65 ma 1 v on input; single input connected to single output 90 ma 10 v on input; eight inputs connected to eight outputs 25 ma operating temperature range industrial (b version) C 40c to +85c automotive (y version) C 40c to +125c storage temp erature range C 65c to +150c junction temperature 150c 32- lead lfcsp_ w q ja thermal impedance 108.2c/w reflow soldering (pb free) peak temperature 260c (+0/ C5) time at peak t emperature 10 sec to 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a str ess rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect devic e reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprie tary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adg2108 data sheet rev. b | page 10 of 28 p in configuration and f unction d escription s nc = no connect y2 y4 y3 y6 y7 y1 y0 y5 nc v dd x9 x8 x7 x6 x5 x4 x1 nc nc nc x3 x2 x0 v ss reset a1 scl a2 a0 sda gnd v l 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 13 14 15 16 12 pin 1 indic a t or adg2108 10 8 t o p view (not to scale) 05898-003 exposed pad dle soldered to v ss figure 3 . pin configuration table 5. p in f unction d escriptions pin no. mnemonic description 1 v ss negative power supply in a dual - supply applicati on. for single - supply applications, this pin should be tied to gnd. 2 to 4 , 23 nc no connect. 5 to 8, 17 to 22 x0 to x9 can be inputs or outputs. 9 to 16 y0 to y7 can be inputs or outputs. 24 v dd positive power supply input. 25 v l logic pow er supply input. 26 sda digital i/o. bidirectional open drain data line. external pull - up resistor required. 27 scl digital input, serial clock line. open drain input that is used in conjunction with sda to clock data into the device. external pul l - up resistor required. 28 a0 logic input. address pin that sets the least significant bit of the 7 - bit slave address. 29 a1 logic input. address pin that sets the second least significant bit of the 7 - bit slave address. 30 a2 logic input. addr ess pin that sets the third least significant bit of the 7 - bit slave address. 31 reset active low logic input. when this pin is low, all switches are open, and appropriate registers are cleared to 0. 32 gnd ground . reference point f or all circuitry on the adg210 8. ep exposed pad. it is recommended that the exposed pad be soldered to v ss to improve heat dissipation and crosstalk.
data sheet adg2108 rev. b | page 11 of 28 typical performance characteristics 200 0 ?5 12 source voltage (v) r on ( ?) 180 160 140 120 100 80 60 40 20 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 11 v ss = ?5v v dd = +5v v ss = 0v v dd = +8v v ss = 0v v dd = +12v t a = 25c i ds = 10ma 05898-007 figure 4 . signal range 85 75 65 55 45 35 25 ?5.5 1.5 0.5 ?0.5 ?1.5 ?2.5 ?3.5 ?4.5 source voltage (v) r on ( ? ) v dd /v ss = 4.5v v dd /v ss = 5v v dd /v ss = 5.5v t a = 25c i ds = 10ma 05898-017 figure 5 . r on vs. source voltage, dual 5 v supplies 70 65 60 55 50 45 40 35 30 25 20 0 8 7 6 5 4 3 2 1 source voltage (v) r on ( ? ) v dd = 12v v dd = 10.8v v dd = 13.2v t a = 25c i ds = 10ma 05898-018 figure 6 . r on vs. supplies, v dd = 12 v 10% 90 80 70 60 50 40 30 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 source voltage (v) r on ( ?) v dd = 8v v dd = 7.2v v dd = 8.8v t a = 25c i ds = 10ma 05898-025 figure 7 . r on vs. source voltage, v dd = 8 v 10% 80 70 60 50 40 30 20 10 0 ?5 1 0 ?1 ?2 ?3 ?4 source voltage (v) r on ( ? ) v dd = +5v v ss = ?5v i ds = 10ma t a = +85c t a = +125c t a = +25c t a = ?40c 05898-026 figure 8 . r on vs. temperature, dual 5 v supplies 60 50 40 30 20 10 0 0 6 5 4 3 2 1 source voltage (v) r on ( ? ) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v i ds = 10ma 05898-027 figure 9 . r on vs. temperature, v dd = 12 v
adg2108 data sheet rev. b | page 12 of 28 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 source voltage (v) r on ( ?) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 8v v ss = 0v i ds = 10ma 05898-013 figure 10 . r on vs. temperature, v dd = 8 v 16 14 12 10 8 6 4 2 0 0 20 40 60 80 100 120 temperature (c) leakage currents (na) x channels, v bias = +4v y channels, v bias = ?2v v dd = +5v v ss = ?5v 05898-014 figure 11 . on leakage vs. temperature, dual 5 v supplies 12 10 8 6 4 2 0 ?2 0 20 40 60 80 100 120 temperature (c) leakage currents (na) x, y channels; v bias = ?2v on x channel; +4v on y channel x, y channels; v bias = +4v on x channel; ?2v on y channel v dd = +5v v ss = ?5v 05898-015 figure 12 . off leakage vs. temperature, dual 5 v supplies 18 12 16 14 10 8 6 4 2 0 ?2 0 20 40 60 80 100 120 temperature (c) leakage currents (na) y channels, v bias = 7v x channels, v bias = 7v y channels, v bias = 1v v dd = 12v v ss = 0v 05898-011 figure 13 . on leakage vs. temperature, 12 v single supply 9 6 8 7 5 4 3 2 1 0 ?1 0 20 40 60 80 100 120 temperature (c) leakage currents (na) x, y channels; v bias = 7v on x channel; 1v on y channel x, y channels; v bias = 1v on x channel; 7v on y channel v dd = 12v v ss = 0v 05898-012 figure 14 . off leakage vs. temper ature, 12 v single supply 0 ?5.0 supply voltage (v) charge injection (pc) ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?3 ?5 ?1 1 3 5 7 9 11 v dd = +5v, v ss = ?5v v dd = +12v, v ss = 0v 05898-030 figure 15 . charge injection vs. supply voltage
data sheet adg2108 rev. b | page 13 of 28 temperature (c) t on / t off (ns) 100 120 140 160 180 200 220 240 ?40 ?20 0 20 40 60 80 100 120 t on t off v dd = 12v, v ss = 0v v dd = +5v, v ss = ?5v 05898-029 figure 16 . t on /t off times vs. temperature ?2 ?8 ?7 ?6 ?5 ?4 ?3 10 1g 10g 10m 100k 1k frequency (hz) insertion loss (db) v dd = +5v v ss = ?5v t a = 25c 05898-020 figure 17 . individual inputs to individual outputs ban dwidth, dual 5 v supply ?1 ?2 ?8 ?7 ?6 ?5 ?4 ?3 10 1g 10g 10m 100k 1k frequency (hz) insertion loss (db) v dd = 12v v ss = 0v t a = 25c 05898-021 figure 18 . individual inputs to individual outputs bandwidth, 12 v single supply 0 ?1 ?2 ?8 ?7 ?6 ?5 ?4 ?3 frequency (hz) insertion loss (db) 10 1g 10g 10m 100k 1k v dd = +5v v ss = ?5v t a = 25c 05898-022 figure 19 . one input to eight outputs bandwidth, 5 v dual supply ?10 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 10 1g 10m 100k 1k frequency (hz) insertion loss (db) v dd = +5v to +12v v ss = ?5v to 0v t a = 25c 05898-023 figure 20 . off isolation vs. frequency ?120 ?100 ?80 ?60 ?40 ?20 10 1g 10m 100k 1k frequency (hz) insertion loss (db) v dd = +5v to +12v v ss = ?5v to 0v t a = 25c adjacent channels non-adjacent channels 05898-024 figure 21 . crosstalk vs. frequency
adg2108 data sheet rev. b | page 14 of 28 0.35 0.05 0.30 0.25 0.20 0.15 0.10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v l = 5v v l = 3v frequency (mhz) i l (ma) v dd = +5v v ss = ?5v 05898-016 figure 22 . digital current (i l ) vs. frequency 1.8 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.2 0 0 6 5 4 3 2 1 v logic (v) i l (ma) v l = 5v v l = 3v 05898-019 figure 23 . digital current (i l ) vs. v logic f or varying digital supply voltage 0 ?120 100 1g frequency (hz) acpsrr (db) ?20 ?40 ?60 ?80 ?100 1k 10k 100k 1m 10m 100m v dd = 5v/12v v ss = ?5v/0v t a = 25c 0.2v p-p ripple switch off, without decoupling switch on, without decoupling with decoupling 05898-028 figure 24 . acpsrr
data sheet adg2108 rev. b | page 15 of 28 test circuits the test circuits show measurements on one channel for clarity, but the circuit applies to any of the switches in the matrix. x y v s r on = v1/i ds i ds v1 05898-031 figure 25 . on resistance x y v x v y i off a a i off 05898-032 figure 26 . off leakage x y v y nc i on a 05898-033 figure 27 . on leakage v x x y v out 50% 90% 9th d at a bit gnd 0. 1f 0. 1f v ss v out v dd v ss v dd c l 35p f r l 300 ? t off and t on 05898-034 figure 28 . switching times, t on , t off xy v x c l 1n f r x q inj = c l v out v out gnd 0.1 f 0.1 f v ss v ss v dd v dd v out sw on d at a bit v out sw off 05898-035 figure 29 . charge injection v x 50? r l 50 ? v x y 0. 1f v s v out off isol a tion = 20 log network ana l yzer 0. 1f v ss v ss 50 ? v dd v dd v out gnd 05898-036 figu re 30 . off isolation v x 50? r l 50 ? v x y 0. 1f v out without switch v out with switch insertion loss = 20 log network ana l yzer 0. 1f v ss v ss v dd v dd v out gnd 05898-037 figure 31 . bandwidth
adg2108 data sheet rev. b | page 16 of 28 y1 y2 x2 v x v out network ana l yzer d at a bit v out r 50? r l 50? 50? r 50? x1 channel- t o-channe l cross t alk = 20 log gnd v s 0.1f 0.1f v dd v dd v ss v ss 05898-038 figure 32 . channel - to - channel crosstalk
data sheet adg2108 rev. b | page 17 of 28 t erminology on resistance (r on ) the series on - channel resistance measured between t he x input/output and the y input/output. on resistance match (?r on ) the channel - to - channel matching of on resistance when channels are operated under identical conditions. on resistance flatness (r flat(on) ) the variation of on resistance over the specifi ed range produced by the specified analog input voltage change with a constant load current. channel off leakage (i off ) the sum of leakage currents into or out of an off channel input. channel on leakage (i on ) the current loss/gain through an on - channel resistance, creating a voltage offset across the device. input leakage current (i in ) the current flowing into a digital input when a specified low level or high level voltage is applied to that input. input off capacitance (c off ) the capacitance between an analog input and ground when the switch channel is off. input/output on capacitance (c on ) the capacitance between the inputs or outputs and ground when the switch channel is on. digital input capacitance (c in ) the capacitance between a digital input a nd ground. output on switching time (t on ) the time required for the switch channel to close. the time is measured from 50% of the logic input change to the time the output reaches 10% of the final value. output off switching time (t off ) the time required for the switch to open. this time is measured from 50% of the logic input change to the time the output reaches 90% of the switch off condition. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitudes plus noise of a signal to th e fundamental. ?3 db bandwidth the frequency at which the output is attenuated by 3 db. off isolation the measure of unwanted signal coupling through an off switch. crosstalk the measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. differential gain the measure of how much color saturation shift occurs when the lu minance level changes. both attenuation and amplification can occur; therefore, the largest amplitude change between any two levels is specified an d is expressed as a percentage of the largest chrominance amplitude. differential phase the measure of how much hue shift occurs when the luminance level changes. it can be a negative or positive value and is expressed in degrees of subcarrier phase. cha rge injection the measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. input high voltage (v inh ) the minimum input voltage for logic 1. input low voltage (v inl ) the maximum input voltage for logic 0 . output low voltage (v ol ) the minimum input voltage for logic 1. input low voltage (v inl ) the maximum output voltage for logic 0. i dd positive supply current. i ss negative supply current.
adg2108 data sheet rev. b | page 18 of 28 theory of operation the adg2108 is an analog cross point switch w ith an array size of 8 10. the 10 rows are referred to as the x input/output lines , and the eight columns are referred to as the y input/output lines. the device is full y flexible in that it connect s any x line or number of x lin es with any y line when t urned on. similarly, it connect s any x line with any number of y lines when turned on. control of the adg2108 is carried out via an i 2 c interface. the device can be operated from single supplies of up to 13.2 v or from dual 5 v supplies. the adg2108 has many attractive features, such as the ability to reset all the switches, the ability to update many switches at the same time , and the option of reading back the status of any switch. all of these features are described in more detail here in the theory of operation section. reset /power - on reset the adg2108 offers the ability to reset all of the 80 switches to the off s tate. this is done through the reset pin. when the reset pin is low , all switches are open (o ff), and appropriate registers are cleared. note that the adg2108 also has a power - on reset block. this e nsures that all swit ches are in the off condition at power - up of the device. in addition , all interna l registers are f illed with 0s and remain so until a valid write to the adg2108 takes place. load switch (ldsw) ldsw is an active high command that allows a number of switches to be simultaneously updated. this is useful in applications where it is important to have synch ronous transmission of signals. there are two ldsw modes: the transparent mode and the latched mode. transparent mode in thi s mode, the switch position change s after the new word is writt en in to the input shift register . ldsw is set to 1. latched mode in this mode , the switch positions are not updated at the same time that the input registers are written to. this is achieved by setting ldsw to 0 for each word (apart from the last word) written to the device. then , setting ldsw to 1 for the last word allows all of the switches in that sequence to be simultaneously updated . readback r ead back of the switch array conditions is also offered when in s tandard mode and fast mode . readback enables the user to check the status of the switches of the adg2108 . this is very useful when debug ging a system .
data sheet adg2108 rev. b | page 19 of 28 serial interface the adg2108 is controlled via an i 2 c- compatible serial bus. the parts are connected to this bus as a slave device (no clock is generated by the switch). h igh speed i 2 c i nterface in addition to stand ard and full speed i 2 c, the adg2108 also supports the high speed (3.4 mhz) i 2 c interface. only the - hs models provide this added performance. see the ordering guide for details. serial bus address the adg2108 has a 7 - bit slave add ress. the four msbs are hard coded to 1110 , and the three lsbs ar e determined by the state of pin a0, pin a1 , and pin a2 . by offering the facility to hardware configure pin a0, pin a1 , and pin a2, up to eight of these devices can be connected to a single s erial bus. the 2 - wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition , defined as when a high - to - low transition on the sda line occurs while scl is high. this indicates that an address/data str eam follows. all slave peripherals conn ected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7 - bit address (msb first) plus an r/ w bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. 2. the peripheral whose address corresponds to the transmitted address responds by pulling the sda line low during the nint h clock pulse, known as the a cknowledge bit. at this stage, all oth er devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is 1 (high), the master read s from the slave device. if the r/ w bit is 0 (low), the master write s to the slave device. 3. data is transmitted over the serial bus in sequences of nine clock pulses: eight data bits followed by an a cknowl - edge bit from the receiver of the data. transitions on the sda line must occur during the low period of the clock signal, scl, and remain stable during the high period of scl because a low - to - high trans ition when the clock is high can be interpreted as a stop signal . 4. when all data bits have been read or written, a stop condition is e stablished by the mast er. a stop condition is defined as a low - to - high transition on the sda line while scl is high. in w rite mode, the master pulls the sda line high during the 10th clock pulse to establish a stop condition. in r ead mode, the master issue s a no acknowledge fo r the ninth clock pulse (that is, the sda lin e remains high). the master then bring s the sda line low before the 10 th clock pulse and then high during the 10th clock pulse to establish a stop condition. refer to figure 33 and figure 34 for a graphical explanation of the serial data transfer protocol.
adg2108 data sheet rev. b | page 20 of 28 writing to the adg21 08 input shift register the input shift register is 24 bits wide. a 3 - byte write is necessar y when writing to this register and is done under the control of the serial clock input, scl. the contents of t he three bytes of the input shift register are shown in figure 33 and described in table 6 . x x x x x x x ldsw db0 (lsb) db7 (msb) data bits data ax3 ax2 ax1 ax0 ay2 ay1 ay0 db8 (lsb) db15 (msb) data bits 1 1 1 0 a2 a1 a0 r/w db16 (lsb) device address db23 (msb) 05898-004 figure 33 . data - wo rds tale 6 . input shift register bit function descriptions bit mnemonic descriptions db23 to db17 1110xxx the msbs of the adg2108 are set to 1110. the lsbs of the address byte are set by the state of the three address pins, pin a0, pin a1 , and pin a2. db16 r/ w controls whether the adg2108 slave device is read from or written to. if r/ w = 1, the adg2108 is being r ead from. if r/ w = 0, t he adg2108 is being written to . d b 15 data controls whether the switch is to be opened (o ff ) or closed (o n). if data = 0 , the switch is opened/o ff . if data = 1, the switch is closed/o n . db14 to db11 a x3 to ax0 control s i/os x0 to x9. see table 7 for the decode truth t able . db 10 to db8 ay2 to ay0 control s i/os y0 to y7. see table 7 for the decode truth t able . db7 to db1 x dont care. db0 ldsw this bit is useful when a number of switches need to be updated simultaneously. if ld sw = 1, the s witch position change s after the new word is read . if ldsw = 0, t he input data is latched, but the switch position is not changed. as shown in table 6 , bit db14 to bit db11 control the x inp ut/output lines, while bit db10 to bit db8 control the y input/output lines. table 7 shows the t ruth table for t hese bits. note that the full coding se quence is written out for channel y0, and channel y1 to channel y7 follow a similar pa ttern. note also that the reset pin must be h igh when writing to the device. table 7. address decode truth table db15 data db14 ax3 db13 ax2 db12 ax1 db11 ax0 db10 ay2 db9 ay1 db8 ay0 switch configuration x 0 0 0 0 0 0 0 reserved x 0 0 0 1 0 0 0 reserved 1 0 0 1 0 0 0 0 x0 to y0 (o n) 0 0 0 1 0 0 0 0 x0 to y0 (o ff ) 1 0 0 1 1 0 0 0 x1 to y0 (o n) 0 0 0 1 1 0 0 0 x1 to y0 (o ff ) 1 0 1 0 0 0 0 0 x2 to y0 (o n) 0 0 1 0 0 0 0 0 x2 to y0 (o ff ) 1 0 1 0 1 0 0 0 x3 to y0 (o n) 0 0 1 0 1 0 0 0 x3 t o y0 (o ff ) x 0 1 1 0 0 0 0 reserved x 0 1 1 1 0 0 0 reserved 1 1 0 0 0 0 0 0 x4 to y0 (on) 0 1 0 0 0 0 0 0 x4 to y0 (off ) 1 1 0 0 1 0 0 0 x5 to y0 (on) 0 1 0 0 1 0 0 0 x5 to y0 (off ) 1 1 0 1 0 0 0 0 x6 to y0 (on) 0 1 0 1 0 0 0 0 x6 to y0 (off ) 1 1 0 1 1 0 0 0 x7 to y0 (on) 0 1 0 1 1 0 0 0 x7 to y0 (off )
data sheet adg2108 rev. b | page 21 of 28 db15 data db14 ax3 db13 ax2 db12 ax1 db11 ax0 db10 ay2 db9 ay1 db8 ay0 switch configuration 1 1 1 0 0 0 0 0 x8 to y0 (on) 0 1 1 0 0 0 0 0 x8 to y0 (off ) 1 1 1 0 1 0 0 0 x9 to y0 (on) 0 1 1 0 1 0 0 0 x9 to y0 (off ) x 1 1 1 0 0 0 0 reserved x 1 1 1 1 0 0 0 reserved x 0 0 0 0 0 0 1 re served x 0 0 0 1 0 0 1 reserved 1 0 0 1 0 0 0 1 x0 to y1 (on) 0 0 0 1 0 0 0 1 x0 to y1 (off ) .. .. .. .. .. .. .. .. 0 1 1 0 1 0 0 1 x9 to y1 (off ) x 0 0 0 0 0 1 0 reserved x 0 0 0 1 1 1 0 reserved 1 0 0 1 0 0 1 0 x0 to y2 (on) 0 0 0 1 0 0 1 0 x0 to y2 (off ) .. .. .. .. .. .. .. .. 0 1 1 0 1 0 1 0 x9 to y2 (off ) x 0 0 0 0 0 1 1 reserved x 0 0 0 1 0 1 1 reserved 1 0 0 1 0 0 1 1 x0 to y3 (on) 0 0 0 1 0 0 1 1 x 0 to y3 (off ) .. .. .. .. .. .. .. .. 0 1 1 0 1 0 1 1 x9 to y3 (off ) x 0 0 0 0 1 0 0 reserved x 0 0 0 1 1 0 0 reserved 1 0 0 1 0 1 0 0 x0 to y4 (on) 0 0 0 1 0 1 0 0 x0 to y4 (off ) .. .. .. .. .. .. .. .. 0 1 1 0 1 1 0 0 x9 to y4 (off ) x 0 0 0 0 1 0 1 reserved x 0 0 0 1 1 0 1 reserved 1 0 0 1 0 1 0 1 x0 to y5 (on) 0 0 0 1 0 1 0 1 x0 to y5 (off ) .. .. .. .. .. .. .. .. 0 1 1 0 1 1 0 1 x9 to y5 (off ) x 0 0 0 0 1 1 0 reserved x 0 0 0 1 1 1 0 reserved 1 0 0 1 0 1 1 0 x0 to y6 (on) 0 0 0 1 0 1 1 0 x0 to y6 (o ff ) .. .. .. .. .. .. .. .. 0 1 1 0 1 1 1 0 x9 to y6 (off ) x 0 0 0 0 1 1 1 reserved x 0 0 0 1 1 1 1 re served 1 0 0 1 0 1 1 1 x0 to y7 (on) 0 0 0 1 0 1 1 1 x0 to y7 (off ) .. .. .. .. .. .. .. .. 0 1 1 0 1 1 1 1 x9 to y7 (off )
adg2108 data sheet rev. b | page 22 of 28 write operation when writing to the adg2108, the user must begin with an address byte and r/ w bit, after which the swit ch a cknowledge s that it is prepared to receive data by pulling sda low. this address byte is followed by the two 8 - bit words. the write operations for the sw itch array are shown in figure 34. note that it is only the condition of the switch corresponding to the bits in the data bytes that change s state. all other switches retain their previous condition. read operation readback on the adg2108 is designed to work as a tool for debug and can be used to output the status of any of the 80 switches of the device. the r eadback fu nction is a two - step sequence that works as follows: 1. select the releva nt x line to be read back from. note that there are e ight switches connecting that x l ine to the eight y lines. the next step involves writing to the adg2108 to tell the part to reveal the status of those eight swit ches . a. enter the i 2 c address of the adg2108, and set the r/ w to 0 to indicat e a write to the device. b. enter the r eadback address for the x line of interest, the addresses of which are shown in table 8 . note that the adg2 108 is expecting a 2 - byte write; therefore , be sure to enter another byte of dont car es ( see figure 35 ). c. the adg2108 t hen places the status of those eight switches in a register than can be read back. 2. the second step involves reading back from the register that holds the status of the eight switches associated with the x line of choice. a. as before, enter the i 2 c address of the adg2108. this time , set the r/ w to 1 to indicate a read back from the device. b. as with a write to the device, the adg2108 outputs a 2 - byte sequence during readback . therefo re , the first eig ht bits of data out that are read back are all 0s. the next eight bits of data that come back are the status of the eight y lines attached to that part icular x line. if the bit is a 1, the switch is closed (on); similarly , if the bit is a 0, the switch is open (off). the entire read sequence is shown in figure 35 . data ax3 ax2 ax1 ax0 ay2 ay1 ay0 a0 r/w a1 a2 x x x x x x x scl sda data byte data byte ack by switch stop cond by master start cond by master address byte ack by switch ack by switch ldsw 05898-005 figure 34 . write operation table 8 . readback addresses for each x line x l ine rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 x0 0 1 1 1 0 1 0 0 x1 0 1 1 1 1 1 0 0 x2 0 0 1 1 0 1 0 1 x3 0 0 1 1 1 1 0 1 x4 0 1 1 1 0 1 0 1 x5 0 1 1 1 1 1 0 1 x6 0 0 1 1 0 1 1 0 x7 0 0 1 1 1 1 1 0 x8 0 1 1 1 0 1 1 0 x9 0 1 1 1 0 1 1 0
data sheet adg2108 rev. b | page 23 of 28 dummy readback byte ack by switch stop cond by master readback byte start cond by master address byte ack by master no ack by master rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 a0 r/w a1 a2 x x x x x x x x scl sda a0 r/w a1 a2 y7 y6 y5 y4 y3 y2 y1 y0 scl sda data byte data byte ack by switch stop cond by master start cond by master address byte ack by switch no ack by switch 05898-006 figure 35 . read operation
adg2108 data sheet rev. b | page 24 of 28 evaluation board the adg21 0 8 evaluation board allows designers to evaluate the high performance adg2108 8 10 switch array with a minimum of effort. the evaluation kit incl udes a populated, tested adg2108 printed circuit board. the evaluation bo ard interfaces to the usb port of a pc , or it can be used as a standalone evaluation board. software is available with the evaluation board that allows the u ser to easily program the adg210 8 through the usb port. schematics of the evaluation board are show n in figure 36 and figure 37. the software runs on any pc that has microsoft? windows? 2000 or windows xp installed. using the adg210 8 evaluation board the adg210 8 evaluation kit is a test system designed to simpl ify the evaluation of the adg210 8. each input/output of the part comes with a socket specifically chosen for easy audio/video evaluation. an application note is also availab le with the evaluation board that gives full information on operating the evaluation board. power supply the adg21 0 8 evaluation board can be operated with both single and dual supplies. v dd and v ss are supplied externally by the user. the v l supply can be applied externally, or the usb port can be used to power the digital circu itr y.
data sheet adg2108 rev. b | page 25 of 28 schematics 05898-041 figure 36 . eval - adg2108eb schematic, usb controller section
adg2108 data sheet rev. b | page 26 of 28 05898-042 figure 37 . eval - adg2108eb schematic, chip section
data sheet adg2108 rev. b | page 27 of 28 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min figure 38 . 32 - lead lead frame chip scale package [lfcsp _w q] 5 mm x 5 mm body, very very thin quad (cp - 32 -7) dimensions shown in millimeters ordering guide model 1 temperature range i 2 c speed package description package option 2 adg2108bcpz - reel7 C 40c to +85c 100 khz, 400 khz 32- lead lead frame chip scale package [lfcsp_ w q] cp - 32 -7 adg2108bcpz - hs - rl 7 C 40c to +85c 100 khz, 400 khz, 3.4 mhz 32- lead lead frame chip scale package [lfcsp_ w q] cp - 32 -7 adg2108ycpz - reel7 C 40c to +125c 100 khz, 400 khz 32 - lead lead frame chip scale pa ckage [lfcsp_ w q] cp - 32 - 7 adg2108ycpz - hs - rl 7 C 40c to +125c 100 khz, 400 khz, 3.4 mhz 32- lead lead frame chip scale package [lfcsp_ w q] cp - 32 -7 eval - adg21 0 8eb z 10 x 8 evaluation board 1 z = rohs compliant part. 2 formerly cp - 32- 2 package.
adg2108 data sheet rev. b | page 28 of 28 notes purchase of licensed i 2 c components of analog devices or on e of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2006 C 2012 analog device s, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05898 - 0 - 9/12(b)

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